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p reliminary p roduct s pecificat ion integrated circuits group lh28f128bfht- pbtl75a flash memory 16mbit (8mbitx16) (model number: lhf12f17) spec. issue date: june 7, 2004

lhf12f17 ? handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ? when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufact ured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). ? office electronics ? instrumentation and measuring equipment ? machine tools ? audiovisual equipment ? home appliance ? communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability , should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, re dundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. ? control and safety devices for airplanes, trains, automobiles, and other transportation equipment ? mainframe computers ? traffic control systems ? gas leak detectors and automatic cutoff devices ? rescue and security equipment ? other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. ? aerospace equipment ? communications equipment for trunk lines ? control equipment for the nuclear power industry ? medical equipment related to life support, etc. (4) please direct all queries and comments regarding the in terpretation of the above three paragraphs to a sales representative of the company. ? please direct all queries regarding the products cove red herein to a sales representative of the company. rev. 0.04
lhf12f17 1 rev. 0.04 contents pa ge 56-lead tsop (normal bend) pinout ....................... 3 pin descriptions.......................................................... 4 simultaneous operation modes allowed with 6 planes........................................ 5 memory map .............................................................. 6 identifier codes and otp address for read operation ............................................. 9 otp block address map for otp program............. 10 bus operation............................................................ 11 command definitions .............................................. 12 functions of block lock and block lock-down..... 14 block locking state transitions upon command write....................................... 14 block locking state transitions upon wp#/acc transition .............................. 15 status register definition......................................... 16 extended status register definition ........................ 18 page 1 electrical specificati ons ........................................ 19 1.1 absolute maximum ratings........................... 19 1.2 operating conditions ..................................... 19 1.2.1 capacitance.............................................. 20 1.2.2 ac input/output test conditions............ 20 1.2.3 dc characteristics................................... 21 1.2.4 ac characteristics - read-only operations............................ 23 1.2.5 ac characteristics - write operations .................................... 27 1.2.6 reset operations...................................... 29 1.2.7 block erase, full chip erase, (page buffer) program and otp program performance ...................... 30
lhf12f17 2 LH28F128BFHT-PBTL75A 128mbit (8mbit 16) page mode dual work flash memory ? 128-m density with 16-bit i/o interface ? high performance reads ? 75/25ns 8-word page mode ? 6-plane dual work operation ? read operations are available during block erase or (page buffer) program between two different planes ? plane architecture: 16m, 24m, 24m, 24m, 24m, 16m ? low power operation ? 2.7v read and write operations ? v ccq for input/output power supply isolation ? automatic power savings mode reduces i ccr in static mode ? enhanced code + data storage ? 5 s typical erase/program suspends ? otp (one time program) block ? 4-word factory-programmed area ? 4-word user-programmable area ? high performance program with page buffer ? 16-word page buffer ? 5 s/word (typ.) at wp#/acc=9.5v ? operating temperature -40 c to +85 c ? cmos process (p-type silicon substrate) ? flexible blocking architecture ? eight 4-kword parameter blocks ? two-hundred and fifty-five 32-kword main blocks ? bottom parameter location ? enhanced data protection features ? individual block lock and block lock-down with zero-latency ? all blocks are locked at power-up or device reset. ? block erase, full chip erase, (page buffer) word program lockout during power transitions ? automated erase/program algorithms ? 3.0v low-power 11 s/word (typ.) programming ? 9.5v no glue logic 9 s/word (typ.) production programming and 0.8s erase (typ.) ? cross-compatible command support ? basic command set ? common flash interface (cfi) ? extended cycling capability ? minimum 100,000 block erase cycles ? 56-lead tsop (normal bend) ? etox tm* flash technology ? not designed or rated as radiation hardened the product, which is 6-plane page mode dual work (simultaneous read while erase/program) flash memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. the product can operate at v cc =2.7v-3.3v. its low voltage operation capability greatly extends battery life for portable applications. the product provides high performance asynchronous page mode. it allows code execution directly from flash, thus eliminating time consuming wait states. the memory array block architecture utilizes enhanced data protection features, and provides separate parameter and main blocks that provide maximum flexibility for safe nonvolatile code and data storage. fast program capability is provided through the use of high speed page buffer program. special otp (one time program) block provides an area to store permanent code such as an unique number. * etox is a trademark of intel corporation. rev. 0.04
lhf12f17 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56-lead tsop standard pinout 14mm x 20mm top view nc nc nc nc 1 2 3 4 56 55 54 53 nc a 22 nc nc a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 20 we# rst# a 21 wp#/acc ry/by# a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 v ccq gnd dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe# gnd ce# a 0 figure 1. 56-lead tsop (normal bend) pinout rev. 0.04
lhf12f17 4 table 1. pin descriptions symbol type name and function a 22 -a 0 input address inputs: inputs for addresses. dq 15 -dq 0 input/ output data inputs/outputs: inputs data and commands during cui (command user interface) write cycles, outputs data during memory array, status register, query code and identifier code reads. data pins float to high-impedance (high z) when the chip or outputs are deselected. data is internally latched during an erase or program cycle. ce# input chip enable: activates the device?s control logic, input buffers, decoders and sense amplifiers. ce#-high (v ih ) deselects the device and reduces power consumption to standby levels. rst# input reset: when low (v il ), rst# resets internal automation and inhibits write operations which provides data protection. rst#-high (v ih ) enables normal operation. after power-up or reset mode, the device is automatically set to read array mode. rst# must be low during power-up/down. oe# input output enable: gates the de vice?s outputs during a read cycle. we# input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of ce# or we# (whichever goes high first). wp#/acc input/ supply write protect: when wp#/acc is v il , locked-down blocks cannot be unlocked. erase or program operation can be executed to the blocks which are not locked and not locked-down. when wp#/acc is v ih , lock-down is disabled. applying 9.5v0.5v to wp#/acc provides fast erasing or fast programming mode. in this mode, wp#/acc is power supply pin. applying 9.5v0.5v to wp#/acc during erase/program can only be done for a maxi mum of 1,000 cycles on each block. wp#/ acc may be connected to 9.5v0.5v for a total of 80 hours maximum. use of this pin at 9.5v+0.5v beyond these limits may reduce block cycling capability or cause permanent damage. ry/by# open drain output ready/busy#: indicates the status of the internal wsm (write state machine). when low, wsm is performing an internal operati on (block erase, full chip erase, (page buffer) program or otp program). ry/by#-high z indicates that the wsm is ready for new commands, block erase is suspended and (page buffer) program is inactive, (page buffer) program is suspended, or the device is in reset mode. v cc supply device power supply (2.7v-3.3v): with v cc v lko , all write attempts to the flash memory are inhibited. de vice operations at invalid v cc voltage (see dc characteristics) produce spurious results and should not be attempted. v ccq supply input/output power supply (2.7v-3.3v): power supply for all input/output pins. gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated. rev. 0.04
lhf12f17 5 notes: 1. "x" denotes the operation available. 2. dual work restrictions: status register reflects wsm (write state machine) state. only one plane can be erased or programmed at a time - no command queuing. commands must be written to an address w ithin the block targeted by that command. table 2. simultaneous operation modes allowed with 6 planes (1, 2) if one plane is: then the modes allowed in the other plane is: read array read id/otp read status read query word program page buffer program otp program block erase full chip erase program suspend block erase suspend read array x x x x x x x x x read id/otp x x x x x x x x x read status x x x x x x x x x x x read query x x x x x x x x x word program x x x x x page buffer program xxxx x otp program x block erase x x x x full chip erase x program suspend xxxx x block erase suspend xxxx x x x rev. 0.04
lhf12f17 6 4-kword block 7 007000h - 007fffh 4-kword block 6 006000h - 006fffh 4-kword block 5 005000h - 005fffh 4-kword block 4 004000h - 004fffh 4-kword block 2 003000h - 003fffh 4-kword block 3 002000h - 002fffh 4-kword block 0 001000h - 001fffh 4-kword block 1 000000h - 000fffh 32-kword block 37 078000h - 07ffffh 32-kword block 35 070000h - 077fffh 32-kword block 33 068000h - 06ffffh 32-kword block 31 060000h - 067fffh 32-kword block 29 058000h - 05ffffh 32-kword block 27 050000h - 057fffh 32-kword block 25 plane0 048000h - 04ffffh 32-kword block 23 040000h - 047fffh 32-kword block 21 038000h - 03ffffh 32-kword block 19 030000h - 037fffh 32-kword block 17 028000h - 02ffffh 32-kword block 15 020000h - 027fffh 32-kword block 13 018000h - 01ffffh 32-kword block 9 010000h - 017fffh 32-kword block 8 008000h - 00ffffh 0f8000h - 0fffffh 0f0000h - 0f7fffh 0e8000h - 0effffh 0e0000h - 0e7fffh 0d8000h - 0dffffh 0d0000h - 0d7fffh 0c8000h - 0cffffh 0c0000h - 0c7fffh 0b8000h - 0bffffh 0b0000h - 0b7fffh 0a8000h - 0affffh 0a0000h - 0a7fffh 098000h - 09ffffh 090000h - 097fffh 088000h - 08ffffh 080000h - 087fffh 32-kword block 38 32-kword block 36 32-kword block 34 32-kword block 32 32-kword block 30 32-kword block 28 32-kword block 26 32-kword block 24 32-kword block 22 32-kword block 20 32-kword block 18 32-kword block 16 32-kword block 14 32-kword block 10 32-kword block 11 32-kword block 12 plane1 32-kword block 69 178000h - 17ffffh 32-kword block 67 170000h - 177fffh 32-kword block 65 168000h - 16ffffh 32-kword block 63 160000h - 167fffh 32-kword block 61 158000h - 15ffffh 32-kword block 59 150000h - 157fffh 32-kword block 57 148000h - 14ffffh 32-kword block 55 140000h - 147fffh 32-kword block 53 138000h - 13ffffh 32-kword block 51 130000h - 137fffh 32-kword block 49 128000h - 12ffffh 32-kword block 47 120000h - 127fffh 32-kword block 45 118000h - 11ffffh 32-kword block 41 110000h - 117fffh 32-kword block 40 108000h - 10ffffh 32-kword block 39 100000h - 107fffh 1f8000h - 1fffffh 1f0000h - 1f7fffh 1e8000h - 1effffh 1e0000h - 1e7fffh 1d8000h - 1dffffh 1d0000h - 1d7fffh 1c8000h - 1cffffh 1c0000h - 1c7fffh 1b8000h - 1bffffh 1b0000h - 1b7fffh 1a8000h - 1affffh 1a0000h - 1a7fffh 198000h - 19ffffh 190000h - 197fffh 188000h - 18ffffh 180000h - 187fffh 32-kword block 70 32-kword block 68 32-kword block 66 32-kword block 64 32-kword block 62 32-kword block 60 32-kword block 58 32-kword block 56 32-kword block 54 32-kword block 52 32-kword block 50 32-kword block 48 32-kword block 46 32-kword block 42 32-kword block 43 32-kword block 44 32-kword block 85 32-kword block 83 32-kword block 81 32-kword block 79 32-kword block 77 32-kword block 75 32-kword block 73 32-kword block 71 32-kword block 86 32-kword block 84 32-kword block 82 32-kword block 80 32-kword block 78 32-kword block 76 32-kword block 74 32-kword block 72 278000h - 27ffffh 270000h - 277fffh 268000h - 26ffffh 260000h - 267fffh 258000h - 25ffffh 250000h - 257fffh 248000h - 24ffffh 240000h - 247fffh 238000h - 23ffffh 230000h - 237fffh 228000h - 22ffffh 220000h - 227fffh 218000h - 21ffffh 210000h - 217fffh 208000h - 20ffffh 200000h - 207fffh [a 22 - a 0 ] [a 22 - a 0 ] plane0 : 16 mbit plane1 : 24 mbit figure 2.1. memory map (bottom parameter, plane 0 and plane 1) rev. 0.04
lhf12f17 7 plane3 32-kword block 165 478000h - 47ffffh 32-kword block 163 470000h - 477fffh 32-kword block 161 468000h - 46ffffh 32-kword block 159 460000h - 467fffh 32-kword block 157 458000h - 45ffffh 32-kword block 155 450000h - 457fffh 32-kword block 153 448000h - 44ffffh 32-kword block 151 440000h - 447fffh 32-kword block 149 438000h - 43ffffh 32-kword block 147 430000h - 437fffh 32-kword block 145 428000h - 42ffffh 32-kword block 143 420000h - 427fffh 32-kword block 141 418000h - 41ffffh 32-kword block 137 410000h - 417fffh 32-kword block 136 408000h - 40ffffh 32-kword block 135 400000h - 407fffh 4f8000h - 4fffffh 4f0000h - 4f7fffh 4e8000h - 4effffh 4e0000h - 4e7fffh 4d8000h - 4dffffh 4d0000h - 4d7fffh 4c8000h - 4cffffh 4c0000h - 4c7fffh 4b8000h - 4bffffh 4b0000h - 4b7fffh 4a8000h - 4affffh 4a0000h - 4a7fffh 498000h - 49ffffh 490000h - 497fffh 488000h - 48ffffh 480000h - 487fffh 32-kword block 166 32-kword block 164 32-kword block 162 32-kword block 160 32-kword block 158 32-kword block 156 32-kword block 154 32-kword block 152 32-kword block 150 32-kword block 148 32-kword block 146 32-kword block 144 32-kword block 142 32-kword block 138 32-kword block 139 32-kword block 140 32-kword block 181 32-kword block 179 32-kword block 177 32-kword block 175 32-kword block 173 32-kword block 171 32-kword block 169 32-kword block 167 32-kword block 182 32-kword block 180 32-kword block 178 32-kword block 176 32-kword block 174 32-kword block 172 32-kword block 170 32-kword block 168 578000h - 57ffffh 570000h - 577fffh 568000h - 56ffffh 560000h - 567fffh 558000h - 55ffffh 550000h - 557fffh 548000h - 54ffffh 540000h - 547fffh 538000h - 53ffffh 530000h - 537fffh 528000h - 52ffffh 520000h - 527fffh 518000h - 51ffffh 510000h - 517fffh 508000h - 50ffffh 500000h - 507fffh [a 22 - a 0 ] plane2 32-kword block 117 32-kword block 115 32-kword block 113 32-kword block 111 32-kword block 109 32-kword block 107 32-kword block 105 32-kword block 103 32-kword block 101 32-kword block 99 32-kword block 97 32-kword block 95 32-kword block 93 32-kword block 89 32-kword block 88 32-kword block 87 32-kword block 118 32-kword block 116 32-kword block 114 32-kword block 112 32-kword block 110 32-kword block 108 32-kword block 106 32-kword block 104 32-kword block 102 32-kword block 100 32-kword block 98 32-kword block 96 32-kword block 94 32-kword block 90 32-kword block 91 32-kword block 92 32-kword block 133 32-kword block 131 32-kword block 129 32-kword block 127 32-kword block 125 32-kword block 123 32-kword block 121 32-kword block 119 32-kword block 134 32-kword block 132 32-kword block 130 32-kword block 128 32-kword block 126 32-kword block 124 32-kword block 122 32-kword block 120 [a 22 - a 0 ] 2f8000h - 2fffffh 2f0000h - 2f7fffh 2e8000h - 2effffh 2e0000h - 2e7fffh 2d8000h - 2dffffh 2d0000h - 2d7fffh 2c8000h - 2cffffh 2c0000h - 2c7fffh 2b8000h - 2bffffh 2b0000h - 2b7fffh 2a8000h - 2affffh 2a0000h - 2a7fffh 298000h - 29ffffh 290000h - 297fffh 288000h - 28ffffh 280000h - 287fffh 3f8000h - 3fffffh 378000h - 37ffffh 370000h - 377fffh 368000h - 36ffffh 360000h - 367fffh 358000h - 35ffffh 350000h - 357fffh 348000h - 34ffffh 340000h - 347fffh 338000h - 33ffffh 330000h - 337fffh 328000h - 32ffffh 320000h - 327fffh 318000h - 31ffffh 310000h - 317fffh 308000h - 30ffffh 300000h - 307fffh 3f0000h - 3f7fffh 3e8000h - 3effffh 3e0000h - 3e7fffh 3d8000h - 3dffffh 3d0000h - 3d7fffh 3c8000h - 3cffffh 3c0000h - 3c7fffh 3b8000h - 3bffffh 3b0000h - 3b7fffh 3a8000h - 3affffh 3a0000h - 3a7fffh 398000h - 39ffffh 390000h - 397fffh 388000h - 38ffffh 380000h - 387fffh plane2 : 24 mbit plane3 : 24 mbit figure 2.2. memory map (bottom parameter, plane 2 and plane 3) rev. 0.04
lhf12f17 8

!"#$ !"#$ figure 2.3. memory map (bottom parameter, plane 4 and plane 5) rev. 0.04
lhf12f17 9 notes: 1. a 22 -a 16 must be the address within the plane to which the read identifier codes/otp command (90h) has been written. 2. block address = the beginning location of a block address within the plane to which the read identifier codes/otp command (90h) has been written. 3. dq 15 -dq 2 are reserved for future implementation. 4. otp-lk=otp block lock configuration. 5. otp=otp block data. table 3. identifier codes and otp address for read operation code address [a 15 -a 0 ] data [dq 15 -dq 0 ] notes manufacturer code manufacturer code 0000h 00b0h 1 device code device code 0001h 0011h 1 block lock configuration code block is unlocked block address + 2 dq 0 = 0 2, 3 block is locked dq 0 = 1 2, 3 block is not locked-down dq 1 = 0 2, 3 block is locked-down dq 1 = 1 2, 3 otp otp lock 0080h otp-lk 1, 4 otp 0081-0088h otp 1, 5 rev. 0.04
lhf12f17 10 customer programmable area lock bit (dq 1 ) factory programmed area lock bit (dq 0 ) customer programmable area factory programmed area reserved for future implementation 000080h 000081h 000084h 000085h 000088h (dq 15 -dq 2) figure 3. otp block address map for otp program (the area outside 80h~88h cannot be used.) [a 22 -a 0 ] rev. 0.04
lhf12f17 11 notes: 1. refer to dc characteristics for v il or v ih voltages. 2. x can be v il or v ih for control pins and addresses. 3. rst# at gnd0.2v ensures the lowest power consumption. 4. command writes involving block erase, full chip erase, (page buffer) program or otp program are reliably executed when v cc =2.7v-3.3v. 5. refer to table 5 for valid d in during a write operation. 6. never hold oe# low and we# low at the same timing. 7. query code = common flash interface (cfi) code. 8. ry/by# is v ol when the wsm (write state machine) is execu ting internal block eras e, full chip erase, (page buffer) program or otp program algorithms. it is high z during when the wsm is not busy, in block erase suspend mode (with program and page buf fer program inactive), (page buffer) program suspend mode, or reset mode. table 4. bus operation (1, 2) mode notes rst# ce# oe# we# address dq 15-0 ry/by# (8) read array 6 v ih v il v il v ih xd out high z output disable v ih v il v ih v ih xhigh zx standby v ih v ih xx xhigh zx reset 3 v il xxx xhigh zhigh z read identifier codes/otp 6 v ih v il v il v ih see table 3 see table 3 high z read query 6,7 v ih v il v il v ih x d out high z read status register 6 v ih v il v il v ih x d out x write 4,5,6 v ih v il v ih v il xd in x rev. 0.04
lhf12f17 12 notes: 1. bus operations are defined in table 4. 2. all addresses which are written at the first bus cycle should be the same as the addresses which are written at the second bus cycle. x=any valid address within the device. pa=address within the selected plane. ia=identifier codes address (see table 3). qa=query codes address. refer to appendix of lh28f128bf series for details. ba=address within the block being erased, set/cleared block lock bit or set block lock-down bit. wa=address of memory location for the program command or the first address for the page buffer program command. oa=address of otp block to be read or programmed (see figure 3). 3. id=data read from identifier codes. (see table 3). qd=data read from query database. refer to appendix of lh28f128bf series for details. srd=data read from status register. see table 9.1, ta ble 9.2 for a description of the status register bits. wd=data to be programmed at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first) during command write cycles. od=data within otp block. data is latched on the rising edge of we# or ce# (whichever goes high first) during command write cycles. n-1=n is the number of the words to be loaded into a page buffer. 4. following the read identifier codes/otp command, read operations access manufacturer code, device code, block lock configuration code and the data within otp block (see table 3). the read query command is available for read ing cfi (common flash interface) information. 5. block erase, full chip erase or (page buffer) program can not be executed when the select ed block is locked. unlocked block can be erased or programmed when rst# is v ih . 6. either 40h or 10h are recognized by the cui (command user interface) as the program setup. table 5. command definitions (11) command bus cycles req?d notes first bus cycle second bus cycle oper (1) addr (2) data oper (1) addr (2) data (3) read array 1 write pa ffh read identifier codes/otp 2 4 write pa 90h read ia or oa id or od read query 2 4 write pa 98h read qa qd read status register 2 write pa 70h read pa srd clear status register 1 write pa 50h block erase 2 5 write ba 20h write ba d0h full chip erase 2 5,9 write x 30h write x d0h program 2 5,6 write wa 40h or 10h write wa wd page buffer program 4 5,7 write wa e8h write wa n-1 block erase and (page buffer) program suspend 1 8,9 write pa b0h block erase and (page buffer) program resume 1 8,9 write pa d0h set block lock bit 2 write ba 60h write ba 01h clear block lock bit 2 10 write ba 60h write ba d0h set block lock-down bit 2 write ba 60h write ba 2fh otp program 2 9 write oa c0h write oa od rev. 0.04
lhf12f17 13 7. following the third bus cycle, input the program sequential address and write data of "n" times. finally, input the any valid address within the target block to be programmed and the confirm command (d0h). 8. if the program operation in one plane is suspended and the er ase operation in other plane is also suspended, the suspended program operation will be resumed first. 9. full chip erase and otp program operations can not be suspended. the otp program command can not be accepted while the block erase operation is being suspended. 10. following the clear block lock bit command, block which is not locked-down is unlocked when wp#/acc is v il . when wp#/acc is v ih , lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 0.04
lhf12f17 14 notes: 1. dq 0 =1: a block is locked; dq 0 =0: a block is unlocked. dq 1 =1: a block is locked-down; dq 1 =0: a block is not locked-down. 2. erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 3. at power-up or device reset, all blocks default to locked state and are no t locked-down, that is, [001] (wp#/acc=0) or [101] (wp#/acc=1), regardle ss of the states before power-off or reset operation. 4. when wp#/acc is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 5. otp (one time program) block has the lock function which is different from those described above. notes: 1. "set lock" means set block lock bit comma nd, "clear lock" means clear block lock bit command and "set lock-down" means set block lock-down bit command. 2. when the set block lock-down bit command is written to the unlocked block (dq 0 =0), the corresponding block is locked-down and automatically locked at the same time. 3. "no change" means that the state remains unchanged after the command written. 4. in this state transitions table, assumes that wp#/acc is not changed and fixed v il or v ih . table 6. functions of block lock (5) and block lock-down current state erase/program allowed (2) state wp#/acc dq 1 (1) dq 0 (1) state name [000] 0 0 0 unlocked yes [001] (3) 001locked no [011] 0 1 1 locked-down no [100] 1 0 0 unlocked yes [101] (3) 101locked no [110] (4) 1 1 0 lock-down disable yes [111] 1 1 1 lock-down disable no table 7. block locking state transitions upon command write (4) current state result after lock command written (next state) state wp#/acc dq 1 dq 0 set lock (1) clear lock (1) set lock-down (1) [000] 0 0 0 [001] no change [011] (2) [001] 0 0 1 no change (3) [000] [011] [011] 0 1 1 no change no change no change [100] 1 0 0 [101] no change [111] (2) [101] 1 0 1 no change [100] [111] [110] 1 1 0 [111] no change [111] (2) [111] 1 1 1 no change [110] no change rev. 0.04
lhf12f17 15 notes: 1. "wp#/acc=0 1" means that wp#/acc is driven to v ih and "wp#/acc=1 0" means that wp#/acc is driven to v il . 2. state transition from the current state [011] to the next state depends on the previous state. 3. when wp#/acc is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 4. in this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. table 8. block locking state transitions upon wp#/acc transition (4) previous state current state result after wp#/acc transition (next state) state wp#/acc dq 1 dq 0 wp#/acc=0 1 (1) wp#/acc=1 0 (1) - [000] 0 0 0 [100] - - [001] 0 0 1 [101] - [110] (2) [011] 0 1 1 [110] - other than [110] (2) [111] - - [100] 1 0 0 - [000] - [101] 1 0 1 - [001] -[110]110 - [011] (3) - [111] 1 1 1 - [011] rev. 0.04
lhf12f17 16 table 9.1. status register definition gwsms gbess gbefces gpbpops gwpaccs gpbpss gdps r 15 14 13 12 11 10 9 8 pwsms gbess gbefces gpbpops gwpaccs gpbpss gdps r 76543210 sr.7 = plane write state machine status (pwsms) 1 = ready 0 = busy sr.6 = global block erase suspend status (gbess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = global block erase and full chip erase status (gbefces) 1 = error in block erase or full chip erase 0 = successful block erase or full chip erase sr.4 = global (page buffer) program and otp program status (gpbpops) 1 = error in (page buffer) program or otp program 0 = successful (page buffer) program or otp program sr.3 = global wp#/acc status (gwpaccs) 1 = v ccq +0.4v < wp#/acc < 9.0v detect, operation abort 0 = wp#/acc ok sr.2 = global (page buffer) program suspend status (gpbpss) 1 = (page buffer) program suspended 0 = (page buffer) program in progress/completed sr.1 = global device protect status (gdps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.0 = reserved for future enhancements (r) notes: status register indicates the status of the wsm (write state machine). however, sr.7 indicates the status of wsm in each plane. even if the sr.7 is "1", the wsm may be occupied by the other plane. in the plane to which the comm and is issued, check sr.7 or ry/by# to determine block er ase, full chip erase, (page buffer) program or otp program completion. sr.6 - sr.1 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of wp#/acc level. the wsm interrogates and indicates the wp#/acc level only after block erase, full chip erase, (page buffer) program or otp program command sequences. sr.3 is not guaranteed to report accurate feedback when wp#/ acc v acch . sr.1 does not provide a continuous indication of block lock bit. the wsm interrogates the block lock bit only after block erase, full chip erase, (page buffer) program or otp program command sequences. it informs the system, depending on the attempted operation, if the block lock bit is set. reading the block lock configuration codes after writing the read identifier codes/otp command indicates block lock bit status. sr.0 is reserved for future use and should be masked out when polling the status register. rev. 0.04
lhf12f17 17 table 9.2. status register definition (continued) sr.15 = global write state machine status (gwsms) 1 = ready 0 = busy sr.14 = global block erase suspend status (gbess) 1 = block erase suspended 0 = block erase in progress/completed sr.13 = global block erase and full chip erase status (gbefces) 1 = error in block erase or full chip erase 0 = successful block erase or full chip erase sr.12 = global (page buffer) program and otp program status (gpbpops) 1 = error in (page buffer) program or otp program 0 = successful (page buffer) program or otp program sr.11 = global wp#/acc status (gwpaccs) 1 = v ccq +0.4v < wpp#/acc < 9.0v detect, operation abort 0 = wp#/acc ok sr.10 = global (page buffer) program suspend status (gpbpss) 1 = (page buffer) program suspended 0 = (page buffer) program in progress/completed sr.9 = global device protect status (gdps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.8 = reserved for future enhancements (r) notes: status register sr.15-sr.9 indicates the status of the wsm. check sr.15 or ry/by# to determine block erase, full chip erase, (page buffer) program or otp program completion. sr.14 - sr.9 are invalid while sr.15="0". if both sr.13 and sr.12 are "1"s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit attempt, an improper command sequence was entered. sr.11 does not provide a continuous indication of wp#/acc level. the wsm interrogates and indicates the wp#/acc level only after block erase, full chip erase, (page buffer) program or otp program command sequences. sr.11 is not guaranteed to report accurate feedback when wp#/ acc v acch . sr.9 does not provide a continuous indication of block lock bit. the wsm interrogates the block lock bit only after block erase, full chip erase, (page buffer) program or otp program command sequences. it informs the system, depending on the attempted operation, if the block lock bit is set. reading the block lock configuration codes after writing the read identifier codes/otp command indicates block lock bit status. sr.8 is reserved for future use and should be masked out when polling the status register. rev. 0.04
lhf12f17 18 table 10. extended status register definition rrrrrrrr 15 14 13 12 11 10 9 8 smsrrrrrrr 76543210 xsr.15-8 = reserved for future enhancements (r) xsr.7 = state machine status (sms) 1 = page buffer program available 0 = page buffer program not available xsr.6-0 = reserved for future enhancements (r) notes: after issue a page buffer program command (e8h), xsr.7="1" indicates that the entered command is accepted. if xsr.7 is "0", the command is not accepted and a next page buffer program command (e8h) should be issued again to check if page buffer is available or not. xsr.15-8 and xsr.6-0 are reserved for future use and should be masked out when polling the extended status register. rev. 0.04
lhf12f17 19 1 electrical specifications 1.1 absolute maximum ratings * operating temperature during read, erase and program ...-40 c to +85 c (1) storage temperature during under bias............................... -40 c to +85 c during non bias................................ -65 c to +125 c voltage on any pin (except v cc , v ccq and wp#/acc) ............................................... -0.5v to v ccq +0.5v (2) v cc and v ccq supply voltage .......... -0.2v to +3.7v (2) wp#/acc supply voltage ......... -0.2v to +10.3v (2, 3, 4) output short circuit current ........................... 100ma (5) *warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes: 1. operating temperature is for extended temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on v cc , v ccq and wp#/acc pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 3. maximum dc voltage on wp#/acc may overshoot to +11.0v for periods <20ns. 4. wp#/acc erase/program voltage is normally 2.7v- 3.3v. applying 9.0v-10.0v to wp#/acc during erase/ program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. wp#/acc may be connected to 9.0v-10.0v for a total of 80 hours maximum. 5. output shorted for no more than one second. no more than one output shorted at a time. rev. 0.04 1.2 operating conditions notes: 1. see dc characteristics tables for voltage range-specific specification. 2. applying wp#/acc=9.0v-10.0v during a erase or program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. a permanent connection to wp#/acc=9.0v-10.0v is not allowed and can cause damage to the device. parameter symbol min. typ. max. unit notes operating temperature t a -40 +25 +85 c v cc supply voltage v cc 2.7 3.0 3.3 v 1 i/o supply voltage v ccq 2.7 3.0 3.3 v 1 wp#/acc voltage when used as a logic control v il -0.2 0.4 v 1 v ih 2.4 v ccq + 0.4 v wp#/acc supply voltage v acch 9.0 9.5 10.0 v 1, 2 main block erase cycling: wp#/acc=v il or v ih 100,000 cycles parameter block erase cycling: wp#/acc=v il or v ih 100,000 cycles main block erase cycling: wp#/acc=v acch , 80 hrs. 1,000 cycles parameter block erase cycling: wp#/acc=v acch , 80 hrs. 1,000 cycles maximum wp#/acc hours at v acch 80 hours
lhf12f17 20 test points v ccq /2 v ccq /2 input v ccq 0.0 output ac test inputs are driven at v ccq (min) for a logic "1" and 0.0v for a logic "0". input timing begins, and output timing ends at v ccq /2. input rise and fall times (10% to 90%) < 5ns. worst case speed conditions are when v cc =v cc (min). device under test r l =3.3k ? c l v ccq (min)/2 out cl includes jig capacitances. 1n914 figure 5. transient equivalent testing load circuit table 11. test configuration capacitance loading value test configuration c l (pf) v cc =2.7v-3.3v 50 1.2.2 ac input/output test conditions 1.2.1 capacitance (1) (t a = + 25 c, f=1mhz) note: 1. sampled, not 100% tested. parameter symbol condition min. typ. max. unit input capacitance c in v in =0.0v 47pf wp#/acc input capacitance c in v in =0.0v 18 22 pf output capacitance c out v out =0.0v 610pf figure 4. transient input/output reference waveform for v cc =2.7v-3.3v rev. 0.04
lhf12f17 21 1.2.3 dc characteristics v cc =2.7v-3.3v symbol parameter notes min. typ. max. unit test conditions i li input load current 1 -1.0 +1.0 a v cc =v cc max., v ccq =v ccq max., v in /v out =v ccq or gnd i lo output leakage current 1 -1.0 +1.0 a i ccs v cc standby current 1,7,8 9 40 a v cc =v cc max., ce#=rst#= v ccq 0.2v, wp#/acc=v ccq or gnd i ccas v cc automatic power savings current 1,3,7 9 40 a v cc =v cc max., ce#=gnd0.2v, wp#/acc=v ccq or gnd i ccd v cc reset current 1,7 9 40 a rst#=gnd0.2v i ccr average v cc read current normal mode 1,6,7 20 30 ma v cc =v cc max., ce#=v il , oe#=v ih , f=5mhz average v cc read current page mode 8 word read 1,6,7 5 10 ma i ccw v cc (page buffer) program current 1,4,6,7 20 60 ma wp#/acc=v il or v ih 1,4,6,7 10 20 ma wp#/acc=v acch i cce v cc block erase, full chip erase current 1,4,6,7 10 30 ma wp#/acc=v il or v ih 1,4,6,7 4 10 ma wp#/acc=v acch i ccws i cces v cc (page buffer) program or block erase suspend current 1,2,6,7 10 200 a ce#=v ih i accs i accr wp#/acc standby or read current 1,5,6,7 2 5 a wp#/acc v cc i accw wp#/acc (page buffer) program current 1,4,5,6,7 2 5 a wp#/acc=v il or v ih 1,4,5,6,7 10 30 ma wp#/acc=v acch i acce wp#/acc block erase, full chip erase current 1,4,5,6,7 2 5 a wp#/acc=v il or v ih 1,4,5,6,7 5 15 ma wp#/acc=v acch i accws wp#/acc (page buffer) program suspend current 1,5,6,7 2 5 a wp#/acc=v il or v ih 1,5,6,7 10 200 a wp#/acc=v acch i acces wp#/acc block erase suspend current 1,5,6,7 2 5 a wp#/acc=v il or v ih 1,5,6,7 10 200 a wp#/acc=v acch rev. 0.04
lhf12f17 22 notes: 1. all currents are in rms unless otherwise noted . typical values are the reference values at v cc =3.0v, v ccq =3.0v and t a =+25 c unless v cc is specified. 2. i ccws and i cces are specified with the device de-selected. if read or (page buffer) program is executed while in block erase suspend mode, the device?s current draw is the sum of i cces and i ccr or i ccw . if read is executed while in (page buffer) program suspend mode, the device?s current draw is the sum of i ccws and i ccr . 3. the automatic power savings (aps) feature automatically places the device in power save mode after read cycle completion. standard address access timings (t avqv ) provide new data when addresses are changed. 4. sampled, not 100% tested. 5. applying 9.5v0.5v to wp#/acc provides fast erasing or fast programming mode. in this mode, wp#/acc is power supply pin and supplies the memory cell current for bloc k erasing and (page buffer) programming. use similar power supply trace widths and layout considerations given to the v cc power bus. applying 9.5v0.5v to wp#/acc during erase/program can only be done for a maximum of 1,000 cycles on each block. wp#/acc may be connected to 9.5v0.5v for a total of 80 hours maximum. 6. the operating current in dual work is the sum of the operating curre nt (read, erase, program) in each plane. 7. for all pins other than those shown in test conditions, input level is v ccq or gnd. 8. includes ry/by#. v il input low voltage 5 -0.4 0.4 v v ih input high voltage 4 2.4 v ccq + 0.4 v v ol output low voltage 4,8 0.2 v v cc =v cc min., v ccq =v ccq min., i ol =100 a v oh output high voltage 4 v ccq -0.2 v v cc =v cc min., v ccq =v ccq min., i oh =-100a v acch wp#/acc during block erase, full chip erase, (page buffer) program or otp program operations 59.09.510.0v v lko v cc lockout voltage 1.5 v v cc =2.7v-3.3v symbol parameter notes min. typ. max. unit test conditions dc characteristics (continued) rev. 0.04
lhf12f17 23 1.2.4 ac characteristics - read-only operations (1) notes: 1. see ac input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. sampled, not 100% tested. 3. oe# may be delayed up to t elqv ? t glqv after the falling edge of ce# without impact to t elqv . 4. address setup time (t av e l , t avgl ) is defined from the falling edge of ce# or oe# (whichever goes low last). 5. address hold time (t elax , t glax ) is defined from the falling edge of ce# or oe# (whichever goes low last). 6. specifications t av e l , t av g l , t elax , t glax and t ehel , t ghgl for read operations apply to only status register read operations. v cc =2.7v-3.3v, t a =-40 c to +85 c symbol parameter notes min. max. unit t avav read cycle time 75 ns t av q v address to output delay 75 ns t elqv ce# to output delay 3 75 ns t apa page address access time 25 ns t glqv oe# to output delay 3 20 ns t phqv rst# high to output delay 150 ns t ehqz , t ghqz ce# or oe# to output in high z, whichever occurs first 2 20 ns t elqx ce# to output in low z 2 0 ns t glqx oe# to output in low z 2 0 ns t oh output hold from first occurring address, ce# or oe# change 2 0 ns t av e l , t avgl address setup to ce#, oe# going low for reading status register 4, 6 10 ns t elax , t glax address hold from ce#, oe# going low for reading status register 5, 6 10 ns t ehel , t ghgl ce#, oe# pulse width high for reading status register 620 ns rev. 0.04
lhf12f17 24 t avqv t ehqz t ghqz t elqv t phqv t glqv t oh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (d/q) (w) (g) (e) (a) a 22-0 dq 15-0 ce# oe# we# rst# high z t elqx valid output valid address t avav t glqx t ghgl t ehel t avel t avgl t glax t elax figure 6. ac waveform for single asynchronous read operations from status register, identifier codes, otp block or query code rev. 0.04
lhf12f17 25 t avqv t elqv t ehqz t ghqz t oh t apa t glqv t phqv high z v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (w) (g) (e) (a) a 22-3 v ih v il (a) a 2-0 (d/q) dq 15-0 ce# oe# we# rst# t glqx t elqx valid address valid address valid address valid address valid output valid output valid output valid output valid address t avav figure 7. ac waveform for asynchronous 4-word page mode read operations from main blocks or parameter blocks rev. 0.04
lhf12f17 26 t avqv t elqv t ehqz t ghqz t oh t apa t glqv t phqv v ih v il v ih v il v ih v il v ih v il v ih v il (p) (w) (g) (e) (a) a 22-3 (a) a 2-0 (d/q) dq 15-0 ce# oe# we# rst# t glqx t elqx valid address t avav v ih v il valid address valid address valid address valid address high z v oh v ol valid output valid output valid output valid output valid address valid address valid address valid address valid output valid output valid output valid output figure 8. ac waveform for asynchronous 8-word page mode read operations from main blocks or parameter blocks rev. 0.04
lhf12f17 27 1.2.5 ac characteristics - write operations (1), (2) notes: 1. the timing characteristics for reading the status register duri ng block erase, full chip erase, (page buffer) program and otp program operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. a write operation can be initiated and terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width (t wp ) is defined from the falling edge of ce# or we# (whichever goes low last) to the rising edge of ce# or we# (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . 5. write pulse width high (t wph ) is defined from the rising edge of ce# or we# (whichever goes high first) to the falling edge of ce# or we# (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 6. t whr0 (t ehr0 ) after the read query or read identifier codes/otp command=t avqv +100ns. 7. refer to table 5 for valid address and data for block erase, full chip erase, (page buffer) program, otp program or lock bit configuration. v cc =2.7v-3.3v, t a =-40 c to +85 c symbol parameter notes min. max. unit t avav write cycle time 75 ns t phwl (t phel ) rst# high recovery to we# ( ce# ) going low 3150 ns t elwl (t wlel ) ce# (we#) setup to we# (ce#) going low 0 ns t wlwh (t eleh ) we# (ce#) pulse width 4 50 ns t dvwh (t dveh ) data setup to we# (ce#) going high 7 40 ns t av w h (t av e h ) address setup to we# (ce#) going high 7 40 ns t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 ns t whdx (t ehdx ) data hold from we# (ce#) high 0 ns t whax (t ehax ) address hold from we# (ce#) high 0 ns t whwl (t ehel ) we# (ce#) pulse width high 5 25 ns t shwh (t sheh ) wp#/acc high setup to we# (ce#) going high wp#/acc=v ih 3 0 ns wp#/acc=v acch 200 t whgl (t ehgl ) write recovery before read 30 ns t qvsl wp#/acc high hold from valid srd, ry/by# high z 3 0 ns t whr0 (t ehr0 ) we# (ce#) high to sr.7 going "0" 3, 6 t avqv +50 ns t whrl (t ehrl ) we# (ce#) high to ry/by# going low 3 100 ns rev. 0.04
lhf12f17 28 t avav t avwh (t aveh ) t whax (t ehax ) t elwl (t wlel ) t phwl (t phel ) t wlwh t whwl (t ehel ) t whdx (t ehdx ) t dvwh (t dveh ) t shwh (t sheh ) t whqv1,2,3 (t ehqv1,2,3 ) t qvsl t wheh (t ehwh )t whgl (t ehgl ) v ih v il v ih v il v ih v il v ih v il v ih v il (d/q) (w) (g) (e) (a) notes 5, 6 a 22-0 dq 15-0 v ih v il (p) rst# ce# oe# we# v ih v il (s) wp# (t eleh ) note 1 note 2 note 3 note 4 note 5 valid address valid address valid address data in data in valid srd notes: 1. v cc power-up and standby. 2. write each first cycle command. 3. write each second cycle command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. for read operation, oe# and ce# must be driven active, and we# de-asserted. ("1") v ol (r) ry/by# (sr.7) high z ("0") (t whr0 (t ehr0 )) t whrl (t ehrl ) notes 5, 6 wp#/acc (s) figure 9. ac waveform for write operations rev. 0.04 v ih , v acch
lhf12f17 29 abort complete t plph t plph t 2vph t plrh t phqv t phqv (a) reset during read array mode (b) reset during erase or program mode (c) rst# rising timing rst# rst# v il v ih v il v ih v cc gnd v cc (min) rst# v il v ih sr.7="1" v oh v ol (d/q) dq 15-0 valid output high z (p) (p) (p) v oh v ol (d/q) dq 15-0 valid output high z v oh v ol (d/q) dq 15-0 valid output high z t phqv t vhqv notes: 1. a reset time, t phqv , is required from the later of sr.7 (ry/by#) going "1" (high z) or rst# going high until outputs are valid. refer to ac characteristics - read-only operations for t phqv . 2. t plph is <100ns the device may still reset but this is not guaranteed. 3. sampled, not 100% tested. 4. if rst# asserted while a block erase, full chip erase, (page buffer) program or otp program operation is not executing, the reset will complete within 100ns. 5. when the device power-up, holding rst# low minimum 100ns is required after v cc has been in predefined range and also has been in stable there. reset ac specifications (v cc =2.7v-3.3v, t a =-40 c to +85 c) symbol parameter notes min. max. unit t plph rst# low to reset during read (rst# should be low during power-up.) 1, 2, 3 100 ns t plrh rst# low to reset during erase or program 1, 3, 4 22 s t 2vph v cc 2.7v to rst# high 1, 3, 5 100 ns t vhqv v cc 2.7v to output delay 31ms figure 10. ac waveform for reset operations 1.2.6 reset operations rev. 0.04
lhf12f17 30 rev. 0.04 1.2.7 block erase, full chip erase, (page buffer) program and otp program performance (3) notes: 1. typical values measured at v cc =3.0v, wp#/acc=3.0v or 9.5v, and t a =+25 c. assumes corresponding lock bits are not set. subject to change based on device characterization. 2. excludes external system-level overhead. 3. sampled, but not 100% tested. 4. a latency time is required from writing suspend command (we# or ce# going high) until sr.7 going "1" or ry/by# going high z. 5. if the interval time from a block erase resume command to a subsequent block erase suspend command is shorter than t eres and its sequence is repeated, the bloc k erase operation may not be finished. v cc =2.7v-3.3v, t a =-40 c to +85 c symbol parameter notes page buffer command is used or not used wp#/acc=v il or v ih (in system) wp#/acc=v acch (in manufacturing) unit min. typ. (1) max. (2) min. typ. (1) max. (2) t wpb 4-kword parameter block program time 2 not used 0.05 0.3 0.04 0.12 s 2 used 0.03 0.12 0.02 0.06 s t wmb 32-kword main block program time 2 not used 0.38 2.4 0.31 1.0 s 2 used 0.24 1.0 0.17 0.5 s t whqv1 / t ehqv1 word program time 2 not used 11 200 9 185 s 2 used 7 100 5 90 s t whov1 / t ehov1 otp program time 2 not used 36 400 27 185 s t whqv2 / t ehqv2 4-kword parameter block erase time 2 - 0.5 4 0.4 4 s t whqv3 / t ehqv3 32-kword main block erase time 2 - 0.9 5 0.8 5 s full chip erase time 2 240 1400 200 1400 s t whrh1 / t ehrh1 (page buffer) program suspend latency time to read 4- 510 510 s t whrh2 / t ehrh2 block erase suspend latency time to read 4- 520 520 s t eres latency time from block erase resume command to block erase suspend command 5-500 500 s
rev. 1.10 i a-1 recommended operating conditions a-1.1 at device power-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a-1. ac timing at device power-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ?electrical specifications? described in specifications for the supply voltage range, the operating temperature and the ac specifications not shown in the next page. t 2vph v cc gnd v cc (min) rp# v il v ih (p) t phqv ce# v il v ih (e) we# v il v ih (w) oe# v il v ih (g) v oh v ol (d/q) data high z valid output t vr t f t elqv t f t glqv (a) address valid (rst#) t r or t f address v il v ih t avqv t r or t f t r t r
rev. 1.10 ii a-1.1.1 rise and fall time notes: 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. symbol parameter notes min. max. unit t vr v cc rise time 1 0.5 30000 s/v t r input signal rise time 1, 2 1 s/v t f input signal fall time 1, 2 1 s/v
rev. 1.10 iii a-1.2 glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). the acceptable glitch noises are illustrated in figure a-2 (a). figure a-2. waveform for glitch noises see the ? dc characteristics ? described in specifications for v ih (min.) and v il (max.). (a) acceptable glitch noises input signal v ih (min.) input signal v ih (min.) input signal v il (max.) input signal v il (max.) (b) not acceptable glitch noises
rev. 1.10 iv a-2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no. document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit

s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e . s u g g e s t e d a p p l i c a t i o n s ( i f a n y ) a r e f o r s t a n d a r d u s e ; s e e i m p o r t a n t r e s t r i c t i o n s f o r l i m i t a t i o n s o n s p e c i a l a p p l i c a t i o n s . s e e l i m i t e d w a r r a n t y f o r s h a r p ? s p r o d u c t w a r r a n t y . t h e l i m i t e d w a r r a n t y i s i n l i e u , a n d e x c l u s i v e o f , a l l o t h e r w a r r a n t i e s , e x p r e s s o r i m p l i e d . a l l e x p r e s s a n d i m p l i e d w a r r a n t i e s , i n c l u d i n g t h e w a r r a n t i e s o f m e r c h a n t a b i l i t y , f i t n e s s f o r u s e a n d f i t n e s s f o r a p a r t i c u l a r p u r p o s e , a r e s p e c i f i c a l l y e x c l u d e d . i n n o e v e n t w i l l s h a r p b e l i a b l e , o r i n a n y w a y r e s p o n s i b l e , f o r a n y i n c i d e n t a l o r c o n s e q u e n t i a l e c o n o m i c o r p r o p e r t y d a m a g e . n o r t h a m e r i c a e u r o p e j a p a n s h a r p m i c r o e l e c t r o n i c s o f t h e a m e r i c a s 5 7 0 0 n w p a c i f i c r i m b l v d . c a m a s , w a 9 8 6 0 7 , u . s . a . p h o n e : ( 1 ) 3 6 0 - 8 3 4 - 2 5 0 0 f a x : ( 1 ) 3 6 0 - 8 3 4 - 8 9 0 3 f a s t i n f o : ( 1 ) 8 0 0 - 8 3 3 - 9 4 3 7 w w w . s h a r p s m a . c o m s h a r p m i c r o e l e c t r o n i c s e u r o p e d i v i s i o n o f s h a r p e l e c t r o n i c s ( e u r o p e ) g m b h s o n n i n s t r a s s e 3 2 0 0 9 7 h a m b u r g , g e r m a n y p h o n e : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 8 6 f a x : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 3 2 w w w . s h a r p s m e . c o m s h a r p c o r p o r a t i o n e l e c t r o n i c c o m p o n e n t s & d e v i c e s 2 2 - 2 2 n a g a i k e - c h o , a b e n o - k u o s a k a 5 4 5 - 8 5 2 2 , j a p a n p h o n e : ( 8 1 ) 6 - 6 6 2 1 - 1 2 2 1 f a x : ( 8 1 ) 6 1 1 7 - 7 2 5 3 0 0 / 6 1 1 7 - 7 2 5 3 0 1 w w w . s h a r p - w o r l d . c o m t a i w a n s i n g a p o r e k o r e a s h a r p e l e c t r o n i c c o m p o n e n t s ( t a i w a n ) c o r p o r a t i o n 8 f - a , n o . 1 6 , s e c . 4 , n a n k i n g e . r d . t a i p e i , t a i w a n , r e p u b l i c o f c h i n a p h o n e : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 4 1 f a x : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 2 6 / 2 - 2 5 7 7 - 7 3 2 8 s h a r p e l e c t r o n i c s ( s i n g a p o r e ) p t e . , l t d . 4 3 8 a , a l e x a n d r a r o a d , # 0 5 - 0 1 / 0 2 a l e x a n d r a t e c h n o p a r k , s i n g a p o r e 1 1 9 9 6 7 p h o n e : ( 6 5 ) 2 7 1 - 3 5 6 6 f a x : ( 6 5 ) 2 7 1 - 3 8 5 5 s h a r p e l e c t r o n i c c o m p o n e n t s ( k o r e a ) c o r p o r a t i o n r m 5 0 1 g e o s u n g b / d , 5 4 1 d o h w a - d o n g , m a p o - k u s e o u l 1 2 1 - 7 0 1 , k o r e a p h o n e : ( 8 2 ) 2 - 7 1 1 - 5 8 1 3 ~ 8 f a x : ( 8 2 ) 2 - 7 1 1 - 5 8 1 9 c h i n a h o n g k o n g s h a r p m i c r o e l e c t r o n i c s o f c h i n a ( s h a n g h a i ) c o . , l t d . 2 8 x i n j i n q i a o r o a d k i n g t o w e r 1 6 f p u d o n g s h a n g h a i , 2 0 1 2 0 6 p . r . c h i n a p h o n e : ( 8 6 ) 2 1 - 5 8 5 4 - 7 7 1 0 / 2 1 - 5 8 3 4 - 6 0 5 6 f a x : ( 8 6 ) 2 1 - 5 8 5 4 - 4 3 4 0 / 2 1 - 5 8 3 4 - 6 0 5 7 h e a d o f f i c e : n o . 3 6 0 , b a s h e n r o a d , x i n d e v e l o p m e n t b l d g . 2 2 w a i g a o q i a o f r e e t r a d e z o n e s h a n g h a i 2 0 0 1 3 1 p . r . c h i n a e m a i l : s m c @ c h i n a . g l o b a l . s h a r p . c o . j p s h a r p - r o x y ( h o n g k o n g ) l t d . 3 r d b u s i n e s s d i v i s i o n , 1 7 / f , a d m i r a l t y c e n t r e , t o w e r 1 1 8 h a r c o u r t r o a d , h o n g k o n g p h o n e : ( 8 5 2 ) 2 8 2 2 9 3 1 1 f a x : ( 8 5 2 ) 2 8 6 6 0 7 7 9 w w w . s h a r p . c o m . h k s h e n z h e n r e p r e s e n t a t i v e o f f i c e : r o o m 1 3 b 1 , t o w e r c , e l e c t r o n i c s s c i e n c e & t e c h n o l o g y b u i l d i n g s h e n n a n z h o n g r o a d s h e n z h e n , p . r . c h i n a p h o n e : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 1 f a x : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 5

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